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Mentor introduces Tessent Safety ecosystem to meet IC test requirements of the autonomous vehicles era

Tessent Safety ecosystem leverages the comprehensive automotive IP portfolio of Arm as part of the company’s Functional Safety Partnership Program

Mentor, a Siemens business, today introduced the new Tessent™ software Safety ecosystem – a comprehensive portfolio of best-in-class automotive IC test solutions from Mentor with links to its industry-leading partners. The program helps IC design teams meet the increasingly stringent functional safety requirements of the global automotive industry.

The Tessent Safety ecosystem provides a robust alternative to competing programs, which are based on closed, monolithic, single-source models. Mentor’s open ecosystem approach to IC test functional safety assurance allows chipmakers to combine Mentor’s industry-leading IC test technologies with other best-in-class solutions, enabling more complete, higher performing end-solutions.

“Fast in-system IC test performance is essential to reducing the time between fault detection and engagement of on-chip safety mechanisms,” said Brady Benware, vice president and general manager for the Tessent product family at Mentor, a Siemens business. “To speed IC test performance, automotive IC designers increasingly need all on-chip safety mechanisms, including DFT and non-DFT technologies, to be closely coupled – and this approach is fundamental to Mentor’s new Tessent Safety ecosystem.”

Planned for rapid expansion via partnerships with Mentor’s deep roster of leading partners, the Tessent Safety ecosystem includes:

  • Industry-leading built-in self-test (BIST) technologies from Mentor, including the new Tessent LBIST with Observation Scan Technology (LBIST-OST) solution designed to dramatically reduce run times for in-system monitoring of digital logic components in automotive ICs. Engineered to help customers meet stringent automotive functional safety requirements, the new Tessent LBIST-OST solution delivers up to a 10x reduction of in-system test time compared to traditional logic BIST technologies.
  • The Tessent™ MemoryBIST, which features a comprehensive automation flow that provides design rule checking, test planning, integration, and verification at either the RTL or gate level. Because Tessent MemoryBIST features a hierarchical architecture, BIST and self-repair capabilities can be added to individual cores as well as at the top level.
  • The Tessent™ MissionMode product, which provides a combination of automation and on-chip IP for enabling semiconductor chips throughout an automotive electronics system to be tested and diagnosed at any point during a vehicle’s functional operation.
  • The Tessent™ DefectSim transistor-level defect simulator for analog, mixed-signal (AMS) and non-scan digital circuits. Ideal for both high-volume and high-reliability ICs, Tessent DefectSim measures defect coverage and tolerance.
  • Mentor’s participation in the Arm® Functional Safety Partnership Program (AFSPP). The Mentor Tessent® Safety ecosystem leverages Arm Safety Ready IP functionalities like the Cortex®-R52 processor, which combines real-time execution with the highest level of integrated functional safety capabilities of any Arm processor, as well as advanced hypervisor technology to simplify software integration, and robust separation functionality to protect safety-critical code.
  • Mentor’s automotive-grade automatic test pattern generation (ATPG) technology, which detects defects at the transistor and interconnect levels often missed by traditional test patterns and fault models.
  • Close links to Mentor’s Austemper SafetyScope and KaleidoScope products, which add state-of-the-art safety analysis, auto-correction and fault simulation technology to address random hardware faults. Austemper technology analyzes a designer’s RTL for faults and vulnerabilities, and is capable of smart fault injection to help safety mechanisms react in a planned manner for covered faults. Through parallelized and distributed operation methods, proprietary acceleration algorithms are used to achieve speed-ups of many orders of magnitude over standard gate-level fault injection techniques.

Please click here to view the full press release.

SOURCE: Mentor

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